During packaging, semiconductor devices typically undergo a number of processing steps to form the complete semiconductor device. Such packaging steps usually include leadframe etching and metal bumping for placement of the semiconductor die placement. These steps are then typically followed by a high temperature die bonding and then a wire bonding process for electrically interconnecting the semiconductor device prior to the completing steps of molding, curing, dicing and curing.
These conventional steps and the typical components used in the packaging process contribute to the overall size and processing cost of the complete semiconductor device package. In particular during etching and metal bumping of the leadframe significant cost and time is incurred depending on the choice of leadframe and etching materials. The resulting metal bump height also contributes to the overall thickness of the semiconductor device. In the die bonding step, the process must be conducted in high temperatures, usually in the range of 300° C. to 430° C., which also contributes to the overall cost in the packaging process. Additionally, exposing the semiconductor device to such high processing temperatures during the package process may contribute to increasing the risk of processing imperfections of the complete semiconductor device. Wire bonding the die for providing electrical interconnects for the semiconductor device typically requires sufficient clearance for the wires above the die and contributes to a significant portion of the overall thickness of the semiconductor device package.
Attempts have been made to reduce the thickness of the die and limit the processing costs in the process steps of packaging semiconductor devices. However, such attempts have lead to other problems. For example, to reduce the overall thickness in conventional leadless design semiconductor devices based on leadframe configurations, limiting the thickness of the die makes the die brittle and makes the die susceptible to damage during die placement. Frequently, damage may include cracks in the die and the like that can result from high compression impact of the die on the leadframe during die placement. Additionally, the wire placement and interconnections formed in the wire bonding process may limit the electrical performance of the semiconductor device and may be a source of semiconductor device failure due to a faulty connection, wire misalignment or short. Such limitations or imperfections may make a finished leadless semiconductor device defective.
Therefore, there is a need for a method of packaging a semiconductor device and a semiconductor device that overcomes or at least alleviates the problems associated with conventional packaging processes of leadless semiconductor devices.